Designing mobile radio frequency (RF) chips (e.g., mobile RF transceivers) is complicated by added circuit functions for supporting communication enhancements. Designing these mobile RF transceivers may include using semiconductor on insulator technology. Semiconductor on insulator (SOI) technology replaces conventional semiconductor (e.g., silicon) substrates with a layered semiconductor-insulator-semiconductor substrate for reducing parasitic capacitance and improving performance. SOI-based devices differ from conventional, silicon-built devices because a silicon junction is above an electrical isolator, typically a buried oxide (BOX) layer. A reduced thickness BOX layer, however, may not sufficiently reduce artificial harmonics caused by the proximity of an active device on the SOI layer and an SOI substrate supporting the BOX layer.
For example, high performance complementary metal oxide semiconductor (CMOS) radio frequency (RF) switch technologies are currently manufactured using SOI substrates. While SOI substrates may provide some protection against artificial harmonics in mobile RF transceivers, SOI substrates are very expensive. Furthermore, increasing device isolation and reducing RF loss may involve expensive handle wafers. For example, a CMOS switch device may be physically bonded to a high resistivity (HR) handle wafer, such as HR-silicon or sapphire. While the increased spatial separation of the switch device from the underlying substrate dramatically improves the RF performance of the CMOS switch, using HR-silicon or sapphire handle wafer dramatically drives up cost. That is, using SOI wafers and handle substrates is quite expensive relative to the cost of a bulk semiconductor wafer.